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| NJU6475B preliminary 12-character 4-line dot matrix low power lcd controller driver with key scan function general description package outline the NJU6475B is a dot matrix lcd controller driver for 12-character 4-line with icon display in single chip. it contains voltage converter, voltage regulator, bleeder resistance, cr oscillator, instruction decoder, character generator rom/ram, high voltage operation controller/driver and key scan circuit. the voltage converter generates (about 8v) from the supply voltage (3v) and regulated by the regulator. the bias level of lcd driving voltage is generated of high value bleeder resistance and the buffer amplifier matches the impedance. 16-step contrast control function is incorporated for its adjustment. therefore, simple power supply circuit and NJU6475B easy contrast adjustment are available. the complete cr oscillator is incorporated without external components for oscillation circuit. the microprocessor interface circuit which operates by 1mhz, can be selected serial interface. the character generator rom consisting of 10,080bits stores 252 kinds of character font. each 160bits cg ram and icon display ram can story 4 kinds of special character to display on the dot matrix display area or 128 kinds of icon on the display area. features 12-character 4-line dot matrix lcd controller driver ? maximum 128-icon display ? serial cpu interface ? display data ram - 48 x 8 bits :maximum 12-character 4-line display ? character generator rom - 10,080 bits:252 characters (5 x 8 dots) ? character generator ram - 32 x 5 bits :4 patterns (5 x 8 dots) ? icon display ram - 32 x 5 bits :maximum 128-icon ? high voltage lcd driver : 37-common/63-segment ? duty & bias ratio : 1/36 duty 1/7bias ? useful instruction set : clear display, return home, display on/off control ? display blink,cursor shift, character shift common and segment driver location order select function (mode-a, mode-b) ? power on reset circuit on chip ? hardware reset ? voltage regulator on chip ? electrical variable resistance on chip ? 32-key scan function (8 x 4 matrix) ? oscillation circuit on chip ? voltage converter (doubler,tripler) on chip ? bleeder resistance on chip ? low oprating current ? operating voltage - 2.4v to 3.6v (except for lcd driving voltage) ? package outline - bumped-chip / tcp ? c-mos technology ?
NJU6475B pad location NJU6475B pad coordinates chip size 11.222.5mm (chip center x=0um,y=0um) pad name pad name x=(um) y=(um) x=(um) y=(um) pad no. pad no. mode a mode b mode a mode b 1 ali-a1 ali-a1 -6240 -1090 51 nc nc 5817 1090 2 osc osc -6020 -1090 52 nc nc 5617 1090 11 3 osc osc -5775 -1090 53 nc nc 5417 1090 22 4 v v -5479 -1090 54 nc nc 5217 1090 55 5 v v -4979 -1090 55 nc nc 5017 1090 ss ss 6 v v -4479 -1090 56 nc nc 4817 1090 5out 5out 7 c2 c2 -3979 -1090 57 nc nc 4617 1090 -- 8 c2 c2 -3479 -1090 58 nc nc 4417 1090 ++ 9 c1 c1 -2979 -1090 59 nc nc 4217 1090 -- 10 c1 c1 -2479 -1090 60 nc nc 4017 1090 ++ 11 v v -1979 -1090 61 nc nc 3817 1090 dd dd 12 vr vr -1479 -1090 62 nc nc 3617 1090 13 v v - 979 -1090 63 nc nc 3417 1090 reg reg 14 test test - 531 -1090 64 segs segs 3160 1090 11 15 sel sel - 302 -1090 65 com com 2780 1090 99 16 - 74 -1090 66 com com 2700 1090 reset reset 10 10 17 p/s p/s 155 -1090 67 com com 2620 1090 11 11 18 rs rs 383 -1090 68 com com 2540 1090 12 12 19 r/w r/w 612 -1090 69 com com 2460 1090 13 13 20 e/scl e/scl 840 -1090 70 com com 2380 1090 14 14 21 1069 -1090 71 com com 2300 1090 lcd/key lcd/key 15 15 22 req req 1298 -1090 72 com com 2220 1090 16 16 23 db /cs db /cs 1536 -1090 73 com com 2140 1090 77 25 25 24 1773 -1090 74 com com 2060 1090 db /sio db /sio 66 26 26 25 db db 2010 -1090 75 com com 1980 1090 55 27 27 26 db db 2247 -1090 76 com com 1900 1090 44 28 28 27 db db 2484 -1090 77 com com 1820 1090 33 29 29 28 db db 2721 -1090 78 com com 1740 1090 22 30 30 29 db db 2958 -1090 79 com com 1660 1090 11 31 31 30 db db 3195 -1090 80 com com 1580 1090 00 32 32 31 k k 3466 -1090 81 segm segm 1500 1090 00 12 32 k k 3632 -1090 82 seg seg 1420 1090 11 160 33 k k 3903 -1090 83 seg seg 1340 1090 22 259 34 k k 4068 -1090 84 seg seg 1260 1090 33 358 35 s s 4244 -1090 85 seg seg 1180 1090 00 457 36 s s 4352 -1090 86 seg seg 1100 1090 11 556 37 s s 4460 -1090 87 seg seg 1020 1090 22 655 38 s s 4568 -1090 88 seg seg 940 1090 33 754 39 s s 4676 -1090 89 seg seg 860 1090 44 853 40 s s 4784 -1090 90 seg seg 780 1090 55 952 41 s s 4892 -1090 91 seg seg 700 1090 66 10 51 42 s s 5000 -1090 92 seg seg 620 1090 77 11 50 43 nc nc 5217 -1090 93 seg seg 540 1090 12 49 44 nc nc 5417 -1090 94 seg seg 460 1090 13 48 45 nc nc 5617 -1090 95 seg seg 380 1090 14 47 46 nc nc 5817 -1090 96 seg seg 300 1090 15 46 47 nc nc 6017 -1090 97 seg seg 220 1090 16 45 48 ali-a2 ali-a2 6217 -1090 98 seg seg 140 1090 17 44 49 ali-b2 ali-b2 6217 1090 99 seg seg 60 1090 18 43 50 nc nc 6017 1090 100 seg seg - 20 1090 19 42 NJU6475B pad name pad name x=(um) y=(um) x=(um) y=(um) pad no. pad no. mode a mode b mode a mode b 101 seg seg - 100 1090 135 seg seg -2820 1090 20 41 54 7 102 seg seg - 180 1090 136 seg seg -2900 1090 21 40 55 6 103 seg seg - 260 1090 137 seg seg -2980 1090 22 39 56 5 104 seg seg - 340 1090 138 seg seg -3060 1090 23 38 57 4 105 seg seg - 420 1090 139 seg seg -3140 1090 24 37 58 3 106 seg seg - 500 1090 140 seg seg -3220 1090 25 36 59 2 107 seg seg - 580 1090 141 seg seg -3300 1090 26 35 60 1 108 seg seg - 660 1090 142 segm segm -3380 1090 27 34 21 109 seg seg - 740 1090 143 com com -3460 1090 28 33 24 24 110 seg seg - 820 1090 144 com com -3540 1090 29 32 23 23 111 seg seg - 900 1090 145 com com -3620 1090 30 31 22 22 112 seg seg - 980 1090 146 com com -3700 1090 31 30 21 21 113 seg seg -1060 1090 147 com com -3780 1090 32 29 20 20 114 seg seg -1140 1090 148 com com -3860 1090 33 28 19 19 115 seg seg -1220 1090 149 com com -3940 1090 34 27 18 18 116 seg seg -1300 1090 150 com com -4020 1090 35 26 17 17 117 seg seg -1380 1090 151 com com -4100 1090 36 25 88 118 seg seg -1460 1090 152 com com -4180 1090 37 24 77 119 seg seg -1540 1090 153 com com -4260 1090 38 23 66 120 seg seg -1620 1090 154 com com -4340 1090 39 22 55 121 seg seg -1700 1090 155 com com -4420 1090 40 21 44 122 seg seg -1780 1090 156 com com -4500 1090 41 20 33 123 seg seg -1860 1090 157 com com -4580 1090 42 19 22 124 seg seg -1940 1090 158 com com -4660 1090 43 18 11 125 seg seg -2020 1090 159 comm comm -4740 1090 44 17 44 126 seg seg -2100 1090 160 comm comm -4820 1090 45 16 33 127 seg seg -2180 1090 161 comm comm -4900 1090 46 15 22 128 seg seg -2260 1090 162 comm comm -4980 1090 47 14 11 129 seg seg -2340 1090 163 coms coms -5085 1090 48 13 11 130 seg seg -2420 1090 164 nc nc -5285 1090 49 12 131 seg seg -2500 1090 165 nc nc -5485 1090 50 11 132 seg seg -2580 1090 167 nc nc -5885 1090 51 10 133 seg seg -2660 1090 168 nc nc -6085 1090 52 9 134 seg seg -2740 1090 169 ali-b2 ali-b2 -6240 1090 53 8 NJU6475B block diagram NJU6475B terminal description pad no. symbol i/o f u n c t i o n 11,5 v ,v - power source : v =+3v gnd : v =0v dd ss dd ss 4 v - lcd driving voltage 5 2,3 osc , i/o system clock terminal 1 osc oscillation c and r are incorporated. (normally open) 2 for external clock operation, the clock should be input on osc . 1 17 p/s i serial input select terminal (fixed to "l") register selection signal input terminal 18 rs i "0" instruction register. (writing) "1" data register. (writing, reading) 19 r/w i read(r) / write(w) selection signal input terminal 20 e/scl i serial clock input terminal 23 db /cs i chip select signal 7 24 db /sio i/o data input terminal (3-state data bus.) 6 25 - 30 db - db i i/o port output terminal 05 22 req o this terminal normally output "l". when confirm a key action, req terminal output puls. 21 lcd/key i fix to "h" level 35 - 42 s -s o key scan signal data output terminal o7 open drain output 31 - 34 k - k i key scan data input terminal 03 in case of non use, fix to "h". 158 - 151 com - com o common signal output terminal 132 65 - 72 150 - 143 73 - 80 162 - 159 comm - o icon common display signal output terminal 1 4 comm 163 coms o static driving common signal output terminal 1 when power down mode v or v levels are output. dd ss 82 - 141 seg - seg o segment signal output terminal 160 81,142 segm ,segm o icon segment driving signal output terminal 12 NJU6475B pad no. symbol i/o f u n c t i o n 57 segs o static driving segment signal output terminal 1 when power down mode v or v level are output. dd ss 10,9 c1 c1 i/o step up voltage capacitor connecting terminal +- +- 8,7 c2 ,c2 6 v o step up voltage output terminal 5out 13 v o voltage regulator output terminal reg connect the resistor between this terminal and vr terminal. 12 vr i reference voltage for voltage regulator input terminal connect the resistor between this reference voltage and v terminal. dd reset terminal 16 reset i when the "l" level input over than 1.2ms to this terminal, the system is reset (at f =180khz). osc common and segment driver location order select terminal. 15 sel i "0" mode a location (see pad coordinates) "1" mode b location (see pad coordinates) 14 test i maker test terminal this terminal should be connected to v (or open.) ss 43 - 47 nc - non connection terminal these terminals are electrically open. 50 - 63 164 - 168 169 ali-a1 alignment mark 49 ali-a2 - these terminals are electrically open. 1ali-b1 48 ali-b2 NJU6475B functional description (1) description for each blocks (1-1) register the NJU6475B incorporates three 8-bit registers, an instruction register (ir), and a data register (dr), key register (kr). the register (ir) stores an instruction code such as "clear display" and "cursor shift" or address data for display data ram (dd ram), character generator ram (cg ram) and icon display ram (mk ram). the mpu can write the instruction code and address data to the register (ir), but it cannot read out from register (ir). the register (dr) is a temporary register, the data stored in the register (dr) is written into dd ram, mk ram. a register from these two registers is selected by the register select signal (rs). register (kr) is an only temporary register for key scan data. this register (kr) can read out the contents when selected key signal at "h" signal. and non relation ship with signal of register select (rs). the relation ship with rs, r/w register as shown below. NJU6475B (1-3-1) the relation between dd ram address and display position on the lcd 12-characters 4-line display - 123 4567 89101112 displayposition 1stline000102030405060708090a0b ddramaddress (hexadecimal) 2ndline101112131415161718191a1b 3rdline202122232425262728292a2b 4thline303132333435363738393a3b when the display shift is performed, the dd ram address changes as follows: [left shift display] (00) 01 02 03 04 05 06 07 08 09 0a 0b 00 (10) 11 12 13 14 15 16 17 18 19 1a 1b 10 (20) 21 22 23 24 25 26 27 28 29 2a 2b 20 (30) 31 32 33 34 35 36 37 38 39 3a 3b 30 [right shift display] 0b 00 01 02 03 04 05 06 07 08 09 0a (0b) 1b 10 11 12 13 14 15 16 17 18 19 1a (1b) 2b 20 21 22 23 24 25 26 27 28 29 2a (2b) 3b 30 31 32 33 34 35 36 37 38 39 3a (3b) (1-4) character generator rom (cg rom) the character generator rom (cg rom) stores 5 x 8 dots character pattern represented in 8-bit character code. the capacity is up to 252 kinds of 5 x 8 dots character pattern. the correspondence between character code and standard character pattern of NJU6475B is shown in table 2. user defined character patterns (custom font) are also available by mask option. (in this case, the address (20) are using for "space pattern".) h NJU6475B NJU6475B (1-5) character generator ram (cg ram) the character generator ram stores any kinds of character pattern in 5 x 8 dots written by the user program to display user's original character pattern. the cg ram can store 4 kinds of character in 5 x 8 dots mode. to display user's original character pattern stored in the cg ram, the address data (00) -(03) should hh be written to the dd ram as shown in table-3. table-3> correspondence of cg ram address, dd ram character code < and cg ram character pattern (5 x 8 dots) character code character pattern cg ram address (dd ram data) (cg ram data) 76543210 76543 210 43210 upper lower bits bits upper lower upper lower 000 0 1111 11 001 000 010 000 characterpattern 11 011 0 example(1) 1111 00000000 01000 100 0 00 11 101 00 0 11 11 110 000 111 00000 cursorposition 11 000 000 001 0 0 0 11 0 1 0 character pattern 11111 011 00 00 example(2) 1 11111 00000001 01001 100 101 00 00 1 110 00 00 1 111 00000 cursorposition 000 001 00000011 01011 100 101 110 111 notes : 1. character code bit 0,1 correspond to the cg ram address bit 3,4 (2bits ; 4patterns). 2. cg ram address 0 to 2 designate character pattern line position. the 8th line should be "0". if there is "1" in the 8th line, but bit "1" is always displayed on the cursor position regardless of cursor existence. 3. row position character pattern correspond to cg ram data bits 0 to 4 are shown above. 4. cg ram character patterns are selected when character code bits 2 to 7 are all "0" and these are addressed by character code bits "0" and "1". 5. "1" for cg ram data corresponds to display on and "0" to display off. NJU6475B (1-6) icon display ram (mk ram) the NJU6475B can display maximum 128 icons. the icon display can be controlled by writing the data into mk ram corresponding to the icons. the relation between mk ram address and icon display position is shown in table-4. table-4> correspondence among icon position, mk ram address and data < mk ram address bits for icon position mk ram address and data hh 76543210 (60-7f) dddddddd 0110000060 ***123497 h 0110000161 ***567898 commlineand h 1 both besides of 1st line 0110010165 ***21222324102 h 0110011066 *******103 (com,com,com,com) h 1357 0110011167 *******104 h 0110100068 ***25262728105 h 0110100169 ***29303132106 commlineand h 2 both besides of 2nd line 011011016d ***45464748110 h 011011106e *******111 (com,com,com,com) h 9111315 011011116f *******112 h 0111000070 ***49505152113 h 0111000171 ***53545556114 commlineand h 3 both besides of 3rd line 0111010175 ***69707172118 h 0111011076 *******119 (com,com,com,com) h 17 19 21 23 0111011177 *******120 h 0111100078 ***73747576121 h 0111100179 ***77787980122 commlineand h 4 both besides of 4th line 011111017d ***93949596126 h 011111107e *******127 (com,com,com,com) h 25 27 29 31 011111117f *******128 h notes : 1. when the icon display function using, the system should be initialized by the software initialization because the mk ram is not initialized by the power on reset and hardware. 2. the cross-points between segments (segm and segm ) and commons (comm to comm and 12 14 com to com ) are always set "off" level. 232 3. in the table 4, * mark are invalid, therefore both of "0" or "1" can be written but these are no meaning. NJU6475B (1-7) timing generator the timing generator generates a timing signals for the dd ram, cg ram and mk ram and other internal circuits. ram and timing for the display and internal operation timing for mpu access are separately generated, so that may not interfere with each other. therefore, when the data write to the dd ram for example, there will be undesirable influence, such as flickering, in areas other than display area. (1-8) lcd driver lcd driver consists of 37-common driver and 63-segment driver. the character pattern data are latched to the addressed segment-register respectively. this latched data controls display driver to output lcd driving waveform. (1-9) cursor blinking control circuit this circuit controls cursor on / off and cursor position character blinking. the cursor or blinking appear in the digit locating at the dd ram address set in the address counter (ac). when the address counter is (08) , h a cursor position is shown as bellow. 6543210 ac ac ac ac ac ac ac ac0001000 4-line display 1 2 3 4 5 6 7 8 9 10 11 12 display position 1stline000102030405060708090a0b ddramaddress (hexadecimal) 2nd line 10 11 12 13 14 15 16 17 18 19 1a 1b 3rdline202122232425262728292a2b 4thline303132333435363738393a3b cursor position note : the cursor or blinking also appear when the address counter (ac) selects the cg ram or the mk ram. but the displayed cursor and blinking are meaningless. if the ac stores the cg or mk ram address data, the cursor and blinking are displayed in the meaning- less position. NJU6475B (2) power on initialization by internal circuits (2-1) internal reset circuits initialization the NJU6475B is automatically initialized by internal power on initialization circuits when the power is turned on. in the internal power on initialization, following instructions are executed. during the internal power on initialization, the busy flag (bf) is "1" and this status is kept during 6ms (f =180khz) after v rose to 2.4v. osc dd initialization sequence set function pd=1 : power down off contrast control set (00) to the contrast register h display on/off d=0 : display off control c=0 : cursor off b=0 : cursor blink off i/d=1 : increment by 1 set mode entry s=0 : non shift clear display end note : if the condition of power supply rise time described in the electrical characteristics is not satisfied, the internal power on initialization will not performed. in this case, the software initialization by mpu is required. (2-2) hardware initialization the NJU6475B prepares reset terminal to initialize the all system. when the "l" level is input over 1.2ms to the reset terminal, reset sequence is executed. in this time, the busy signal is output during 6ms (f =180khz) after reset terminal went to "h". osc -timing chart over 1.2ms external reset signal 6ms busy NJU6475B (3) instruction the NJU6475B incorporates two registers, an instruction register (ir) and a data register (dr). these two registers store control information temporarily to allow interface between NJU6475B and mpu or peripheral ic operating different cycles. the operation of NJU6475B is determined by this control signal from mpu. the control information includes resister selection signals (rs), read / write signals (r/w) and data signal (sio). NJU6475B (3-1) description of each instructions (a) maker test 76543210 rsr/wdbdbdbdbdbdbdbdb code0000000000 (b) clear display 76543210 rsr/wdbdbdbdbdbdbdbdb code0000000001 clear display instruction is executed when the code "1" is written into db . 0 when this instruction is executed, the space code (20) is written into every dd ram address, then h the dd ram (00) is set into address counter and i/d of entry mode is set as increment mode. if the cursor h or blink are displayed, they are returned to the left end of the 1st line on the lcd panel. in addition, s of entry mode is not changes and contents of mk ram and cg ram are also not changed. note : the character code (20) must be blank code in the user defined character pattern (custom font). h (c) return home 76543210 rsr/wdbdbdbdbdbdbdbdb code000000001**=don'tcare return home instruction is executed when the code "1" is written into db . 1 when this instruction is executed, the dd ram address (00) is set into the address counter. display is h returned to its original position if shifted, the cursor or blink are returned to the left end of the 1st line on the lcd if the cursor or blink are operating. the dd ram contents do not change. (d) entry mode set 76543210 rsr/wdbdbdbdbdbdbdbdb code00000001i/ds entry mode set instruction which sets the cursor moving direction and display shift on/off, is executed when the code "1" is written into db and codes of (i/d) and (s) are written into db (i/d) and db (s). 2 10 (i/d) sets the address increment or decrement, and the (s) sets the entire display shift at the dd ram writing. i/d function 1 address increment : the address of the dd ram or cg ram increment (+1) when the read/write operation, and the cursor or blink moves to the right. 0 address decrement : the address of the dd ram or cg ram decrement (-1) when the read/write operation, and the cursor or blink moves to the left. sfunction entire display shift. the shift direction is determined by i/d. : shift to left at i/d=1 and shift to the right at 1 the i/d=0. the shift is operated only for the character, so that it looks as if the cursor stands still and display moves. the display does not shift when reading from dd ram and writing/reading into/from cg ram. 0 the display does not shift. NJU6475B (e) display on/off control 76543210 rsr/wdbdbdbdbdbdbdbdb code0000001dcb display on/off control instruction which controls the whole display on/off, the cursor on/off and the cursor position character blink, is executed when the code "1" is written into db and codes of (d), (c) 3 and (b) are written into db (d), db (c) and db (b), as shown below. 21 0 dfunction 1 display on 0 display off. in this mode, the display data remains in the dd ram so that it is retrieved immediately on the display when the d changes to 1. cfunction 1 cursor on. the cursor is displayed by 5 dots on the 8th line. 0 cursor off. even if the display data write, the i/d etc does not change. bfunction the cursor position character is blinking. 1 blinking rate is 480ms at f =180khz. osc the cursor and the blink can be displayed simultaneously. 0 the character does not blink. character font 57 dots alternating display (1) cursor display example (2) brink display example (f) cursor display shift 76543210 rsr/wdbdbdbdbdbdbdbdb code 0 0 0 0 0 1 s/c r/l * * *= don't care the cursor /display shift instruction shifts the cursor display to the right or left without writing or reading display data. this function is used to correct or search the display. the cursor moves to the 2nd line after the 12nd digit of the 1st line. notice that 1st to 3rd line displays shift at the same time. when the displayed data are shifted repeatedly, each display moves in only same line. the 2nd and 3rd line display do not shift intothe1stand2ndline. the contents of address counter (ac) does not change by operation of only the display shift. this instruction is executed when the code "1" is written into db and the codes of (s/c) and (r/l) are 4 written into db (s/c) and db (r/l), as shown below. 32 s/c r/l f u n c t i o n 0 0 shift the cursor position to the left ((ac) is decremented by 1). 0 1 shift the cursor position to the right ((ac) is incremented by 1). 1 0 shifts the entire display to the left and the cursor follows it. 1 1 shifts the entire display to the right and the cursor follows it. NJU6475B (g) function set 76543210 rsr/wdbdbdbdbdbdbdbdb code00001****pd*=don'tcare function set instruction which sets the interface data length and power down is executed, when the code "1" is written into db and (pd) is written into db , as shown below. 50 when the power down mode is set, the display turns off automatically. afterward, when the power down mode is reset, the display is off continuously. the display appears by the display on instruction. pd f u n c t i o n 1 power down mode off (normal operation) 0 power down mode on (the display goes to off automatically.) (h) set electronic volume register 76543210 rsr/wdbdbdbdbdbdbdbdb code0 0 0 1 * *cccc*=don'tcare 3210 higher order bit lower order bit contrast control instruction which adjusts the contrast of lcd, is executed when the code "1" is written into db and the codes of c to c are written into db to db as shown below. 60303 the contrast of lcd can be adjusted one of 16 voltage stage by setting 4 bit register. set the binary code "0000" when contrast control unused. 3 2 1 0 lcd lcd dd 5 c ccc vv=v-v 0000low : : 1111high NJU6475B (i) set ram address 76543210 rsr/wdbdbdbdbdbdbdbdb code0 0 1 aaaaaaa higher order bit lower order bit the ram address set instruction is executed when the code "1" is written into db and the address is 7 written into db to db as shown above. 60 the address data (db to db ) is written into the address counter (ac) by this instruction. 60 after this instruction execution, the data writing/reading is performed into/from the addressed ram. the ram includes dd ram, cg ram and mk ram and these rams are shared by addressed as shown below. ram address hh dd ram 1st line : (00) to (0b) hh dd ram 2nd line : (10) to (1b) hh dd ram 3rd line : (20) to (2b) hh dd ram 4th line : (30) to (3b) hh cg ram 4 characters : (40) to (5f) hh mk ram 128 icons : (60) to (7f) (j) write data to cg, dd or mk ram -write data to dd ram 76543210 rsr/wdbdbdbdbdbdbdbdb code1 0 dddddddd higher order bit lower order bit -write data to cg or mk ram 76543210 rsr/wdbdbdbdbdbdbdbdb code1 0 * * * ddddd*=don'tcare higher order bit lower order bit write data to ram instruction is executed when the code "1" is written into (rs) and code "0" is written into (r/w). by the execution of this instruction, the data is written into ram. the selection of ram is determined by the previous instruction. after this instruction execution, the address increment (+1) or decrement (-1) is performed automatically according to the entry mode set. NJU6475B (3-2) initialization using the internal reset circuit when internal reset operates for initialization, the function set, display on/off control and entry set instruc- tion must be executed before the data input as shown below. initialized power on no display appears 76543210 rs r/w db db db db db db db db functionset 00001****1powerdownmodeoff turn on display and cursor. displayon/off 0000001110entiredisplayisinspace control mode. in case of mark dis- play function, the contens of mk ram should be ini- tialized by instruction be- fore the display on. example for address incre- entrymodeset 0000000110entandcursorrightshift when the data is written to the dd, cg or mk ram. write data to the dd, cg or mk ram and set the instruction NJU6475B (3-3) initialization by instruction if the power supply conditions for the correct operation of the internal reset circuits are not met, the NJU6475B must be initialized by instruction. initialized power on no display appears wait more than 6ms after v rises to 2.4 v dd 76543 210 rs r/w db db db db db db db db functionset 00001***** wait more than 3.0ms functionset 00001***** wait more than 200us functionset 00001***** set operation and power functionset 00001***** downmodeoff. displayoff 00001***** displayclear 00001***** example for address incre- entrymodeset 00001***** mentandcursorrightshift when the data is written to the dd, cg or mk ram. write data to the dd, cg or mk ram note : when the icon display function using, the contents and set the instructions of mk ram should be initialized by instruc- tion before the display on. NJU6475B (4) power down function NJU6475B incorporates the power down mode to reduce the operating current. the power down mode is set/reset by the function set instruction. in the power down mode, all the character display and icon display turn off and only static display operation is available. the status of internal circuits at the power down mode is shown below. -main oscillator stops and sub oscillator for the static display starts the operation. -voltage converter, key scan, voltage regulator, voltage follower (op-amp) are stopped. -the contents of dd, cg, mk ram are kept. (5) lcd display (5-1) power supply for lcd driving NJU6475B incorporates voltage converter to generate the lcd driving voltage which is adjusted by the voltage regulater and the evr. (a) voltage converter -voltage tripler by connecting capacitor between c1 and c1 , c2 and c2 , v and v respectively, two times +-+- ss 5out negative voltage of v --v output from v . dd ss 5out -voltage doubler +- + by connecting capacitor between c2 and c2 , v and v respectively, and connecting the c1 ss 5out terminal to c2 terminal, and c1 terminal being open, negative voltage of v --v output from v . +- dd ss 5out v =+3v v =+3v dd dd v=0v v =0v ss ss v=-3v 5out voltage doubler v = -6v 5out voltage tripler (b) voltage regulator voltage regulator incorporates a op-amp which is supplied v and v , and a reference voltage dd 5out source (v ). ref by setting the vr level by connecting ra and rb, the regulator which amplifies v , outputs the lcd ref driving voltage to the v terminal. reg therefore the lcd driving voltage can be output between v and v by setting. dd reg reg ref dd reg 5out v = ( 1+ rb / ra) v in condition, v = 0v, v < v the evr functions v value adjustment from 1st step to 16th by a step when the 4 bit data write into the ref evr register by the instruction. set the evr register to (00) when the evr function is unused. use variable resistances to external to the h external resistances ra, rb and thermistor if need due to the voltage reference v is changed by the lot ref and operating temperature. take care the noise input on the vr terminal because of it is designed with high impedance. short wiring should be required to avoid the noise input, if necessary. NJU6475B [ the voltage reference v characteristics ] ref supply voltage : v = 0v, v = -3v temperature : 25 c dd ss [ the lcd operating voltage v characteristics ] reg supply voltage : v = 0v, v = -3v, voltage tripler output : v = -9v dd ss 5out external resistances : ra = 180k rb = 820k temperature : 25 c ?? , reg h ref h used formulation : v (xx) = (1 + 820k /180k ) v (xx) ?? -8 -7 -6 -5 elec tric v olume v alue vreg(v) 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch0dh 0eh 0fh 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 0dh 0eh 0fh electric volume value -1.3 -1.25 -1.2 -1.15 -1.1 -1.05 vref(v) NJU6475B (c) bleeder resistance each lcd driving voltage (v , v , v , v , v ) is generated by the high impedance bleeder resistance 12345 buffered by voltage follower op-amp to get a enough display characteristics with low operating current. the bleeder resistance is set 1/7 bias suitable for 1/36 duty by 5m resistance in total. ? the capacitor connected between v and v is needed for stabilizing v . the determination of the each 5dd 5 capacitance of c , c and c generating for lcd operating voltage is required to operate with the lcd 12 3 panel actually. the capacitance for the typical application is shown below: lcd driving voltage vs duty power duty ratio 1/36 supply bias 1/7 lcd dd 5 vv-v v is the maximum amplitude for lcd driving voltage. lcd typical application for lcd operating voltage generation note : take care the noise into the vr terminal as designed with high impedance. short wiring or sealed wiring are required to avoid the noise, if necessary. NJU6475B (5-2) relation between oscillation frequency and lcd frame frequency as the NJU6475B incorporates oscillation capacitor and resistor for cr oscillation, 180khz oscillation is available without any external components. (1 clock = 5.56us) 1/36 duty 1 frame = 5.56 (us) x 62 x 36 = 12.4 (ms) frame frequency = 1 / 12.4 (ms) = 80.6 (hz) NJU6475B (6) key scan circuit (6-1) key scan timing chart chattering chattering 03 ktok continuously 3 times "l" detection continuously 3 times "h" detection keycheck (innerside hhhlllkeycheck 0.71ms keycheck lhhlhhh keycheck of NJU6475B) fig. 1 req fig. 2 lcd/key r/w db7/cs lcd data(write) e/scl set key register (inner side set "00010000 00000000" into register of NJU6475B) "hi-z" 07 stos fig. 4 fig. 3 (6-2) key scan 1. keycheck signal always operates to check the status of keys excepting for power down mode. 2. when key signal (k to k ) 3 times detected continuously at rise up edge of keycheck (inner side 03 nju6475), key scan circuit performs output request signal (req terminal) rise to "h" and simultaneously key input information transmit to cpu. its useful for anti-chattering. at the same time of req signal output, the key register status is "00010000 00000000" (non key input) automatically. key input terminal (k to 0 k ) are "h" in normal, then turn to "l" when key input. 3 chattering 03 ktok continuously 3 times "l" detection keycheck (innerside hhhlll 0.71ms of NJU6475B) req fig. 1 in case of request signal "h", when detects 3 times continuously key released status, request signal will be "l". chattering 03 ktok continuously 3 times "h" detection keycheck (innerside lhhlhhh of NJU6475B) req fig. 2 NJU6475B 3. when the request signal is detected, cpu should be lcd / key to "h" and read out key data by instruc- tion. 16-bit key data synchronizing to "scl" (scl terminal) is read out to cpu. (1st time output key data was fixed as "00010000 00000000") keyscan operation start from the next rising edge of scl after the end of key data read out opration. fig. 3 4. the key data are gotten from 4 terminals (k to k ) at each timing of key scan signals (s to s ). 03 07 the detected data are up dating anytime and stores to key register. 0 s "l" 1 s 7 s 0.45ms fig. 4 end of key scan - key scan timing : 0.45ms (fosc = 180khz,max =0.64ms) - pulth width : 45us (fosc = 180khz, max =64us) NJU6475B (6-3) key scanning timing key status is gotten at 3/4 port timing of t during "l" period of s to s . kp 0 7 0 s kp t 1 s 1/4 t kp 3/4 t kp detecting timing (6-4) the format of detection 1st byte 2nd byte msb lsb msb lsb l3 l2 l1 l0 h7 h6 h5 h4 h3 h2 h1 h0 0001 kkkk kkkkkkkk fix l3 l0 3 0 h7 h0 7 0 k to k : corresponds to k to k k to k : corresponds to s to s ( for example ) 1st byte 2nd byte msb lsb msb lsb 00011100 00000100 NJU6475B (6-5) key roll over input NJU6475B can be accepted the key roll over input. in case of key roll over input, the output results are shown below; -connecting same s signal line at multiple key push. x when key-in shown above case, the data contents are "00011100" "00000100". the case of connecting different s signal line at multiple key push (1) - x when key-in shown above case, the data contents are "00010100" "00010100". NJU6475B -the case of connecting different s signal line at multiple key push (2) x when key-in like as shown above, the data contents are "00010101" "00010100". in this case, the result will be same, at each key-in shown below. [case 1] [case 2] [case 3] [case 4] [case 5] [case 6] NJU6475B (6-6) the inner composition of key scan circuit the inner composition of key scan circuit shown below : n j u 6 4 7 5 b inner circuit output nch o o o o input pull up open drain schmitt 01 7 0123 ss s kkkk -in case of non input the key each terminal status shown below: s to s : the status of nch fet output side is on, output result is "l". 07 k to k : the status is "h" by pull-up resistance. 03 -when any key key-in, k of key-in side turn to "l" and it can confirms. x -input terminal (k to k ) are composed by schmitt inverter input method. 03 NJU6475B (7) interface with mpu interface circuit of NJU6475B can be connected to serial by turn to "l" p/s terminal on shown below serial data timing. and db to db can be use to output port. 05 notes : rs, r/w, lcd/key requires setting before cs fall down. rs is unrelated to read out of key data and writing of port data. serial interface circuit is in operation at cs is "l". when scl rises, input data was lead, and rises cs case loading input data. when the input data was less than 16 bits, input data will be invalid at rises cs. and so on equal or over than 16 bits case, rear side total 16 bits are effectiveness. the input data should be total 16 bits. the data of read/write are composed msb first. NJU6475B data format - the data formatted by 2 byte form at read/write. when writing data consists lcd data and port data. the using data in write mode means one of key data. in write mode of data format, 1st byte means recognition data of lcd data and port data. in "0110 0000" (fixed) selects lcd data, in "0110 0001" (fixed) selects port data. the data of 2nd byte consists each data contents. when the 1st byte of msb 4 bit data are not "0110", in this case the input data will be invalid. * * dddddddddbdbdbdbdbdbdbdb 76543210 76543210 lcd/ rs r/w key 1st byte 2nd byte higher lower 0 0 0 selected bit selected bit lcd data (instruction) instruction lcd (0110) (0000) execution data time higher lower 0 1 0 selected bit selected bit lcd data (ram data) instruction lcd (0110) (0000) execution data time higher lower output port (set "l"=0,"h"=1) selected bit selected bit instruction port 0 * 0 (0110) (0001) execution data d d d d d d ** time b b b b b b 5 4 3 2 1 0 key data 1 key data 2 selected bit k k k k k k k k k k k k key 1 * 1 (0001) l l l l h h h h h h h h data 3 2 1 0 7 6 5 4 3 2 1 0 * : invalid data notes : the instruction requires execution time after transmit 16 bit data. after transmit data can not transmit continuously NJU6475B maximum absolute ratings p a r a m e t e r symbol r a t i n g s unit n o t e supply voltage (1) v - 0.3 ~ + 7.0 v dd input voltage v - 0.3 ~ v + 0.3 v tdd operating temperature topr - 30 ~ + 80 c storage temperature tstg - 55 ~ + 125 c note-1 : if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. note-2 : decoupling capacitor should be connected between v and v due to the stabilized operation for dd ss the voltage converter. note-3 : all voltage value are specified as v = 0v. ss the relation : v > v , v > v v , v = 0v must be maintained. dd ss dd ss 5out ss NJU6475B electrical characteristics (v = 2.4 ~ 3.6v, ta = -20 ~ +75 c) dd symbol unit note parameter conditions min. typ. max. v0.8v-vv4 ih1 0 3 dd dd (osc1, except terminals k k ) ~ input voltage 1 vv-0.2vv4 il1 0 3 ss dd (osc1, except terminals k k ) ~ v0.8v-vv4 ih2 0 3 dd dd (application to terminals ) kk ~ input voltage 2 vv-0.2vv4 il2 0 3 ss dd (application to terminals ) kk ~ v (applicate to terminal osc1) v -0.5 - v v 4 ih3 dd dd input voltage 3 v (applicate to terminal osc1) v - 0.5 v 4 il3 ss v -i = 0.205ma, v = 3.0v 2.0 - - v 5 oh1 oh dd output voltage 1 v i = 1.6ma, v = 3.0v - - 0.5 v 5 ol1 ol dd output voltage (s ~ s ) v i = 300ua - - 0.6 v 07 ol2 ol driver on-resist (com) r i = 1ua (all com terminal) - - 20 k 8 com1 d ? odd5 v=v,v driver on-resist (seg) r i = 1ua (all seg terminal) - - 30 k 8 seg1 d ? odd5 v=v,v driver output-resist r i = 1ua (all com terminal) - - 40 k 8 com2 d ? o14 (com) v = v , v driver output-resist r i = 1ua (all seg terminal) - - 50 k 8 seg2 d ? o23 (seg) v = v , v iv v sink current - - -12.3 ua 11 driver current iv v source current 16.8 - - ua 44 input leak current ili v = 0 ~ v -1 - 1 ua 6 in dd pull-up mos current -ip 10 25 50 ua v = 3v (all db, terminal) dd 0 3 kk ~ i320380ua7 dd1 osc f = internal osc on display v = 3v, on display, v = -5v dd 5 operating current i-640ua7 dd2 osc f = internal osc on display v = 3v on access, t = 5us dd cyce , voltage output v v = 3v i 3 times -4.6 -4.8 v 5out dd out voltage ta = 25c = 100ua converter voltage v r = 3 times 90.0 95.0 % ef l part efficiency v ta = 25c 2.44 2.57 2.70 1 v v = 3v 2.01 2.14 2.27 2dd lcd drive voltage v v v = 0v 0.73 0.86 0.99 35 v measured at com/seg 0.30 0.43 0.56 4 terminal bleeder resistance ? r (v - v )/ib r v - v = 3v 5.0 bdd5 b dd5 m i :bleeder resistance cur. b r : 5 bleeder resist b output voltage v v -10.8 - v -1.8 reg l rv 5out dd dd r= ,r =1m ,v =-10.8v ? reg. operating voltage v v reference v -11 - v -3.6 v 5out dd dd dd reference voltage v v reference, ta=25c v -0.75 v -1.05 v -1.35 ref dd dd dd dd clock oscillation freq. f v = 3v, ta=25c 125 180 235 khz osc dd lcd driving voltage v v terminal, v = 3v v -3 - v -13.5 v 9 lcd 5out dd dd dd NJU6475B note-4 : input/output structure except lcd display are as shown below. -input terminal structure (without pull-up mos) (pull-up with mos, schmitt) (pull down mos) applicated terminals : e/scl, rs, k ~ k test 03 r/w, p/s, sel, reset, lcd/key -input terminals structure applicated terminal : osc1 -common terminals input/output structure. applicated terminal 70 :db todb NJU6475B note-5 : apply to the output and input/output terminals. note-6 : except current of pull-up mos and output drive mos. note-7 : except input/output part current but including the current on bleeder resistance. if the input level is medium, current consumption will increase due to penetration current. therefore, the input level must be fixed to "h" or "l". operating current measurement circuit - note-8 : rcom and rseg are the resistance values between power supply terminals (v , v ) and dd 5out each common terminal (com to com / comm to comm ) and supply voltage (v , 132 1 4 dd v ) and each segment terminal (seg to seg / segm to segm ) respectively, and 5out 160 1 2 measured when the current id is flown on every common and segment terminals at same time. note-9 : apply to the voltage from each com and seg are less than 0.15v against the lcd driving contrast voltage (v , v ) at no load condition. dd 5out NJU6475B bus timing characteristics -serial interface sequence (v =2.4~3.6v,v =0v,ta=-20~+75c) dd ss p a r a m e t e r symbol min. max. condition unit serial clock cycle time t 1 - fig. 1 us cyce serial clock "high" level t 300 - fig. 1 ns sch width "low" level t 700 - fig. 1 ns scl serial clock rise and fall down time t , t - 20 fig. 1 ns scr scf chip select pulse width pw 500 - fig. 1 ns cs chip select set up time t 200 - fig. 1 ns csu chip select hold time t 300 - fig. 1 ns ch chip select rise and fall time t , t - 20 fig. 1 ns csr csf set up time rs, r/w, lcd/key-cs t 200 - fig. 1 ns as address hold time t 200 - fig. 1 ns ah serial input data set up time t 200 - fig. 1 ns sisu serial input data hold time t 200 - fig. 1 ns sih serial output data delay time t - 700 fig. 1 ns sod serial output data hold time t 200 - fig. 1 ns soh serial interface fig. 3 serial interface sequence characteristics NJU6475B -i/o part sequence parameter symbol min. max. conditon unit port set time t - 500 fig. 2 us ps theloadofdb todb iscl=100pf - 07 cs ih1 v ih1 v 05 db ~ db ps il1 tv fig. 2 i/o port sequence (serial interface) -the input conditions of using hardware reset circuit. input timing rsl t reset vil parameter symbol condition min. typ. max. unit reset input raw level width t - 1.2 - - ms rsl the power supply conditions of using power on reset circuit. - (ta = -20 ~ +75c) parameter symbol condition min. typ. max. unit the power supply rise time t - 0.1 - 5 ms rdd the power off time t - 1 - - ms off since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case of initialized by instruction. (refer to initialization by the instruction) t specifies the power off time in a short period off or cyclical on/off. off * t specifies the power off time in a short period off or cyclical on/off. off NJU6475B key scan sequence - p a r a m e t e r symbol min. typ. max. condition unit e/scl-s to s delay time t - 66.7 300 fig. 3 us 07 kds key scan pulse width "h","l" level t - 44.4 48 fig. 3 us kp key scan time t - 0.36 0.38 fig. 3 ms ks req output delay time t - - 1.0 fig. 3 us kdr key in check signal frequency t 0.98 1.41 1.84 fig. 3 khz kf -the load of k to k is cl = 20 pf 03 dd dd 0.7v 0.7v dd dd keycheck 0.5v 0.5v kf 1/t dd 0.7v dd req 0.3v kdr kdr tt ih1 scl/e v kds t 0 s 1 s 2 s 3 s 4 s 5 s kp t 6 s 7 s ks t fig. 3 key scan sequence NJU6475B -external clock input p a r a m e t e r symbol min. max. condition unit external clock operating frequency f 125 235 fig. 4 khz cp external clock duty duty 45 55 fig. 4 % external clock rise time t - 0.2 fig. 4 us cpr external clock fall time t - 0.2 fig. 4 us cpf cp tf ki k tt t duty = ki t+t osc1 v-0.5 dd dd cp cp 0.5v tf = 1/f v+0.5 dd cpf cpr tt fig.4 external clock input -the key scan circuit timing characteristics measurement cricurit NJU6475B s(s ) k(k ) 01~7 01~3 ? note : sw resistance is 0 cl=20pf (measurement : only pattern wires) NJU6475B lcd driving wave form NJU6475B application circuit (1) 12-character 4-line (terminal description, mode a) NJU6475B application circuit (2) 12-character 4-line (terminal description, mode b) n j u 6 47 5 b m e m o [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. |
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